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dc.contributor.author Aghdasi, F.
dc.contributor.author Bhasin, A.
dc.date.accessioned 2010-11-04T12:29:02Z
dc.date.available 2010-11-04T12:29:02Z
dc.date.issued 2004
dc.identifier.citation Aghdasi,F. and Basin, A.(2004) Self-clocked sequential circuits:a design example, Botswana Journal of Technology, Vol. 13, No. 1, pp.18-25 en_US
dc.identifier.issn 1019 1593
dc.identifier.uri http://hdl.handle.net/10311/648
dc.description.abstract Asynchronous sequential circuits offer improved speed of operation when compared to their synchronous counterparts. However, the standard methods of asynchronous design require careful examination of the flow table for possible critical races and hazards. This complicates the design procedure and often leads to extra states and additional hardware. A number of new design methodologies which involve locally generating a clock and using it to self synchronize the machine have been proposed. Such clock signals are generated wherever an input changes, or by controlled excitation whenever a change of inputs necessitates a change of state. All such designs, where the circuit is timed by locally generated clocks, are called Self-Clocked Sequential Circuits. This paper uses a design methodology for the State variable toggling through data driven clocks to implement a Direct Memory Access Controller (DMAC) as a design example. The design is simulated on software and also implemented using discrete hardware components. The methodology can be extended to parallel controllers for neutral networks and automated using state assignment techniques already for synchronous parallel controllers. en_US
dc.language.iso en en_US
dc.publisher University of Botswana en_US
dc.subject Sequential circuits en_US
dc.subject Synchronous en_US
dc.subject Asynchronous en_US
dc.subject Neutral networks en_US
dc.title Self-clocked sequential circuits: a design example en_US
dc.type Published Article en_US
dc.rights.holder University of Botswana en_US


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