Browsing Faculty of Engineering and Technology by Author "Bhasin, A."
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Aghdasi, F.; Bhasin, A. (University of Botswana, NaN, 2004)[more][less]
Abstract: Asynchronous sequential circuits offer improved speed of operation when compared to their synchronous counterparts. However, the standard methods of asynchronous design require careful examination of the flow table for possible critical races and hazards. This complicates the design procedure and often leads to extra states and additional hardware. A number of new design methodologies which involve locally generating a clock and using it to self synchronize the machine have been proposed. Such clock signals are generated wherever an input changes, or by controlled excitation whenever a change of inputs necessitates a change of state. All such designs, where the circuit is timed by locally generated clocks, are called Self-Clocked Sequential Circuits. This paper uses a design methodology for the State variable toggling through data driven clocks to implement a Direct Memory Access Controller (DMAC) as a design example. The design is simulated on software and also implemented using discrete hardware components. The methodology can be extended to parallel controllers for neutral networks and automated using state assignment techniques already for synchronous parallel controllers. URI: http://hdl.handle.net/10311/648 Files in this item: 1
Aghdasi_BJT_2004.pdf (1.145Mb)
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